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| THURSDAY, June 10, 2004, 10:30 AM - 12:00 PM | Room: 6C | ||
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TOPIC AREA: PHYSICAL CIRCUIT DESIGN | ||
| SESSION 43 | |||
| Timing Issues in Placement | |||
| Chair: Bill Halpin - Intel Corp., Santa Clara, CA | |||
| Organizers: Carl Sechen, Phiroze Parakh | |||
| This session presents algorithmic improvements in performance-driven physical synthesis. This includes buffering and logic replication, as well as a new timing-driven placement algorithm. | |||
 43.1 |
Modeling Repeaters Explicitly within Analytical Placement |
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| Speaker(s): | Prashant Saxena - Intel Corp., Hillsboro, OR | ||
| Author(s): | Prashant Saxena - Intel Corp., Hillsboro, OR Bill Halpin - Synplicity, Inc., Sunnyvale, CA | ||
| 43.2 | Quadratic Placement Using an Improved Timing Model | ||
| Speaker(s): | Bernd Obermeier - Technical Univ. of Munich, Munich, Germany | ||
| Author(s): | Bernd Obermeier - Technical Univ. of Munich, Munich, Germany Frank M. Johannes - Technical Univ. of Munich, Munich, Germany | ||
| 43.3 | An Approach to Placement-Coupled Logic Replication | ||
| Speaker(s): | Milos Hrkic - Univ. of Illinois, Chicago, IL | ||
| Author(s): | Milos Hrkic - Univ. of Illinois, Chicago, IL John Lillis - Univ. of Illinois, Chicago, IL Giancarlo Beraudo - Univ. of Illinois, Chicago, IL | ||
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